Memory technologies can be used to store information in the form of patterns. To check that a stored pattern (e.g., a reference pattern) matches a pattern provided at some input terminal (e.g., a target pattern), it is typical to first read the reference pattern and then compare the target pattern with the reference pattern. Comparison of the target pattern with the reference pattern can yield a “yes” or a “no” matching level. FIG. 1A illustrates a conventional memory-based system to perform pattern checking. Referring to FIG. 1A, a reference pattern is stored in a memory array, and, in order to perform a comparison with a target pattern, the reference pattern is first read from the memory array. Reading the reference pattern from the memory array takes at least a few clock cycles and introduces undesirable latencies into the system. Also, comparison between the target pattern and the reference pattern is typically performed in another part of the system that is separate from the memory array, such as a crypto-processor section. As a result, the reference pattern (once read from the memory array) has to be conveyed to another part of the system, such as via a data bus. Conveyance of the reference pattern not only introduces additional latencies but also renders the reference pattern susceptible to interception or tampering while in transit.
It is against this background that a need arose to develop the apparatus, system, and method described herein.